This invention relates to a nonvolatile semiconductor memory device (EEPROM : Electrically Erasable Programmable ROM) including memory cell units in which a plurality of electrically rewritable memory cells are connected.
A NAND type EEPROM has been known as a kind of EEPROM enabling electrical rewriting. A single memory cell of NAND type EEPROM has a FETMOS (Floating gate Electrically erasable Tunneling MOS) structure stacking a floating gate (charge storage layer) and a control gate on a semiconductor substrate via an insulating film. A plurality of memory cells are connected in series while sharing common source and drain between every adjacent ones thereof to form a NAND type memory cell unit (hereinafter simply called NAND cell). Such NAND cells are arranged in form of a matrix to make up a memory cell array.
Drains at one-side ends of NAND cells aligned in the column direction of a memory cell array are commonly connected to a bit line via a selection gate transistor, and sources at the other common ends are connected to a common source line via a selection gate transistor, here again. Word lines of memory transistors and gate electrodes of selection transistors are commonly connected in the column direction of the memory cell array as a word line (control gate line) and a selection gate line, respectively.
This kind of NAND type EEPROM is known from the following literatures (1) and (2), for example.
(1) K. D. Suh, et al., "A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme," IEEE J. Solid-State Circuits, Vol. 30, pp. 1149-1156, November 1995
(2) Y. Iwata et al., "A 35 ns Cycle Time 3.3V Only 32Mb NAND Flash EEPROM," IEEE J. Solid-State Circuits, Vol. 30, pp. 1157-1164, November 1995.
FIG. 14 shows configuration of a single NAND cell block in a memory cell array of NAND cell type EEPROM. A plurality of memory cells M are connected in series while sharing common source and drain between every adjacent ones thereof to form a NAND type memory cell unit. An end of each NAND cell is connected to a bit line BL via a selection transistor S1, and the other end thereof is connected to a common grounded line via a selection transistor S2. Control gates of memory cells M aligned in the horizontal direction in FIG. 14 are commonly connected to a word line WL. Similarly, gates of the selection transistors S1 and S2 are commonly connected to selection gate lines SSL and GSL, respectively. The range of NAND cells driven by a single word line makes up a NAND cell block.
In general, a plurality of such NAND cell blocks are arranged in the bit line direction to form a memory cell array. Each NAND cell block is the minimum unit for data erasure, and so-called flash erasure (collective erasure) is conducted therefore. A series of memory cells aligned along a single selected word line within the NAND cell block is called one page, and one page is the unit for reading and writing data.
Each memory cell M stores data by representing the status with a positive threshold value due to injection of electrons into the floating gate (E(Enhancement) type status) and the status with a negative threshold value due to discharge of electrons from the floating gate (D(Depletion) type status) by using two values, respectively. For example, it is determined that the D type status is the status holding "1" data (erasure mode) and the E type status is the status holding "0" data (write mode). Additionally, it is defined that the operation shifting the threshold value of a memory cell holding "1" data toward the positive direction and changing it into the status holding "1" data is "write operation", and operation shifting the threshold value of a memory cell holding "0" data toward the negative direction and changing it into the status holding "1" data is "erase operation". In this specification, explanation is progressed according to such definition.
FIG. 15 shows relations among voltages of different portions data erase, read-out, write operations in a selected NAND cell block of a memory cell array. In erase operation, all word lines in a selected NAND cell block are set in 0V, and the selection gate lines SSL, GSL and bit line BL are held floating (F). Then a high positive erase voltage Vera (for example, erase pulse of 3ms and 21V) to P-type wells of memorycells. As a result, in the selected block, an erase voltage is applied between wells and word lines, and electrons are released from the floating gate to the wells by a FN(Fowler-Nordheim) tunneling current. Consequently, memory cells in the NAND cell block become the erase mode of "1".
At that time, in non-selected NAND cell blocks, there are no influences from the erase pulse because of capacity coupling of floating-status word lines and wells. The coupling ratio is calculated from the capacitance connected to word lines under the floating status. Actually, capacities of poly-silicon word lines and P wells in cell regions occupy an overwhelming part of the whole capacity, and the coupling ratio obtained from a result of actual measurement is as large as about 0.9 and disturbs the flow of FN tunneling current. For verifying erasure, it is judged whether threshold voltage has become -1V or lower in all memory cells in the selected block.
Data read-out operation is effected by applying 0V to the selected word line and a predetermined intermediate voltage Vread (a voltage independent from the threshold value and large enough to render the channel conductive) to non-selected word lines and selection gate lines, and by reading changes in potential of the bit lines BL caused by conduction or non-conduction of the selected memory cells.
Data write operation is effected by applying a positive high write voltage Vpgm to the selected word line, an intermediate voltage Vpass to non-selected word lines, Vcc to the selection gate line SSL on the part of bit lines, and Vss=0V to the selection gate line GSL on the part of common source line, and applying Vss to bit lines BL to write "0" in, and Vcc to bit lines prohibited to write (that is, bit lines to be maintained in the erase mode of "1"). At that time, in a selected memory cell connected to the bit line supplied with Vss, the channel potential is held in Vss, a large electric field between the control gate and the channel is applied, and electrons are injected from the channel to the floating gate due to a tunneling current. In the other non-selected memory cells connected to the same bit line and applied with vpass, electric field is not sufficient for writing. Therefore, writing is not effected.
In memory cells along a bit line applied with Vcc, channels of the NAND cell are pre-charged to Vcc or Vcc-Vth (Vth is the threshold voltage of the selection transistor), and the selection transistor is cut of f. Then, when the write voltage Vpgm and the intermediate voltage Vpass are applied to the control gates, the channel potential increases due to capacity coupling between the NAND cell channels in the floating status and the control gates applied with Vpgm or vpass, and electron injection does not occur.
In this manner, only in the memory cell at the crossing point of the bit line applied with Vss and the selected word line applied with Vpgm, electrons are injected, and "0" is written. In memory cells prohibited to write in within the selected block, since the channel potential is determined by capacity coupling between word lines and channels, in order to apply a sufficiently high write prohibiting voltage, it is important to ensure sufficient initial charging of channels and increase the capacity coupling ratio between word lines and channels.
Coupling ratio B between word lines and channels is calculated by B=Cox/(Cox+Cj) where Cox and Cj are the lump sum of gate capacities between word lines and channels and the lump sum of junction capacities of sources and drains of memory cell transistors, respectively. Channel capacity of a NAND cell is the total of this gate capacity lump sum Cox and the junction capacity lump sum Cj. The other capacities, such as overlap capacity of selection gate lines and sources, capacity of bit lines and sources/drains, etc., are very small as compared with the capacity of all channels, they are disregarded here.
The issue of scaling in the above-explained NAND type EEPROM is next explained with reference to FIG. 16. FIG. 16 shows relations between the number of memory cells in a NAND cell and the ratio of the effective memory cell area per bit over the area of one memory cell, taking the memory capacity as a parameter. A feature of NAND type EEPROM lies in that the effective memory size can be reduced as a result of common use of two selection gate transistors and contacts of bit lines and source lines by a plurality of memory cells.
In case of 0.4 .mu.m rule, 64Mb NAND type EEPROM, the number of memory cells in a NAND cell is 16, and the ratio of the effective memory cell area per bit over the area of one memory cell was 1.20 as shown in FIG. 16. In 0.2 .mu.m rule, 256 Mb NAND type EEPROM, if the number of memory cells in a NAND cell is 16 equally, the ratio of the effective memory cell area per bit over the area of one memory cell is 1.26. Further, in a 0.13 .mu.m rule, 1Gb NAND EEPROM, assuming the number of memory cells being 16 here again, this ratio is estimated to become 1.33.
A reason why the ratio of the effective memory cell area over the actual memory cell area increases with miniaturization and increase of the capacity lies in that, although the pitch of word lines (width of each word line+space) can be reduced in accordance with the design rule, it makes it difficult to reduce contact areas of the selection transistors as overheads with the bit lines and the source lines. This is caused, in one aspect, from difficulty of the process for making minute contacts, etc., but in the other aspect, there is another reason attendant to the device design, namely, miniaturization being limited by the need for a margin for write operation. Whichever the reason is, when the number of memory cells in a NAND cell is limited to 16, the effective memory size increases from that of 64 Mb as a reference by 5% (1.12/1.20=1.05) in case of 256 Mb and by 11% (1.33/1.20=1.11) in case of 1 Gb.
In contrast, when the number of memory cells in a NAND cell of 1Gb NAND type EEPROM is increased to 32, the ratio of the effective memory cell area per bit over the area of one memory cell decreases to 1.17, and the chip size decreases to 88%. However, this is applicable when the area of a chip occupied by the memory cell array is assumed to be 60% in both cases. However, increasing memory cells in each NAND cell invites other problems.
The first one of the problems is that the block size of flash erasure of data is doubled. However, this is mainly a problem concerning the specification, and can be removed. For example, capacity required for one shot of a digital camera of 300,000 pixels is about 0.5 Mb, and it corresponds to the capacity of four blocks of 16 kilobytes. However, as the capacity of digital cameras increases to 1.3 million pixels or 2 million pixels, the number of blocks necessary for one shot increases when the block size is fixed to 16 kilobytes. Such increase of blocks leads to the problem of decreasing the writing speed of one shot. Therefore, in certain cases, EEPROM is desired to increase the block size to a certain level along with an increase of its capacity.
The second one of the problems is that doubling the number of memory cells results in reducing the memory cell current by half. When the memory cell current reduces by half, the bit line sensing time during read-out operation, namely, the time from selection of a word line to activation of a sense amplifier is doubled. If the number of memory cells in a NAND cell is 16, ion case of 1 Gb, it is planned that the bit line capacity is 3.4 pF, the bit line amplitude is 0.7V, and the memory cell current is 0.5 .mu.A, and in this case, the bit line sensing time is 4.65 .mu.s. If memory cells in a NAND cell are increased from 16 to 32 under the condition that the bit line capacity does not change, the bit line sensing time becomes 9.52 .mu.s.
Such increase of the bit line sensing time not only increases the random read-out time but also causes the write time to increase. Specification of the random read-out time normally becomes about a double of the bit line sensing time because the time of entering a command and an address, the time for selecting a word line, the time for outputting data and their margins are added to the bit line sensing time. If the device is designed to include 16 memory cells in a NAND cell, the random read-out time can be limited within 10 .mu.s. Since a write pulse is about 20 .mu.s, the write cycle time is about 30 .mu.s (10 s+20 .mu.s). Therefore, in the case where writing is completed by six write cycles, the write time is 30 .mu.s.times.6=180 .mu.s. In contrast, if the device is designed to include 32 memory cells in a NAND cell, since the random read-out time becomes 20 .mu.s, the write cycle time is about 40 .mu.s, and the write time is 40 .mu.s.times.6=240 .mu.s.
Therefore, when the write time is fixed to 200 .mu.s as the specification, the write cycle has to be limited to 5 or less. For this purpose, load to a process, like the need for minimizing fluctuation of the coupling ratio of memory cells, increases. If improvement of the process cannot be expected, specification of the write time, for example, has to be relaxed from 200 .mu.s to 300 .mu.s. This is a great hazard against progressing the feature of NAND type EEPROM, i.e., high-speed rewriting.
NAND EEPROM rewrites data by FN tunneling over the entire surface of a channel, which is different from writing by hot electron injection employed by NOR type EEPROM and erasure at the source side by using band-to-band tunneling. Therefore, a large number of memory cells can be rewritten simultaneously. As a result, when the time for loading data to be written is disregarded, the writing throughput can be doubled and quadrupled by increasing the writing page size from 512 bytes to 1 kilobyte and further to 2 kilobytes. By making use of the feature of high-speed rewriting, applications of NAND type EEPROM are being extended to voice (voice recorder), images (digital still camera), audio and moving pictures. However, if the verify read-out speed after data write decreases because of reduction of the cell current and it results in a decrease of the page writing speed, applications of NAND EEPROM will be limited.
The random read-out time does not matter so much even if it increases from 10 .mu.s to 20 .mu.s, for example. That is, since NAND type EEPROM is not a device intended or random bit processing but a device intended for block data processing, the speed of queue search is not important. For example, when a mass of data over 16 pages is to be read out, a random read-out time is required as the time for queue search to read out the first one page. However, for the second page, et seq., by executing sequential page read-out (a mode for progressing the sensing operation of the next page in parallel with read-out operation of the preceding page), no time for random read-out is required upon movement from page to page.